SK Hynix DRAM: 1c generation DDR5 chips are fully developed

Every DRAM manufacturer wants to be the first in new manufacturing processes. Now SK Hynix is ​​aiming to win the race in the so-called “1c” DRAM. According to its own information, SK Hynix is ​​the first manufacturer to have fully developed DDR5 DRAM, which is now the sixth generation of the 10nm class.

However, series production will not begin until the end of this year. Larger quantities of the new DDR5 chips with a storage capacity of 16 gigabits (2 GB) are expected by 2025.

Faster, cheaper, more economical

The new process is intended to represent an expansion of the 1b platform. Thanks to a new material and the optimization of the EUVprocess, manufacturing costs should be “more competitive.” In addition, productivity, i.e. the production of chips per wafer, will increase by 30 percent thanks to an improved design.

To reduce potential errors arising from the process advancement procedure and transfer the advantage of 1b, which is widely applauded for its better-performing DRAM, in the most efficient way, the company expanded the 1b DRAM platform for the development of 1c.

The new product comes with an improvement in cost competitiveness compared to the previous generation by adopting a new material in a certain extreme ultraviolet, or EUV, process while optimizing the overall EUV application process. SK hynix also improved productivity by more than 30% through technological innovation in design.

The operating speed of 1c DDR5, which is expected to be adopted for high-performance data centers, has improved by 11% over the previous generation to 8Gbps. With power efficiency also improved by over 9%, SK hynix expects the adoption of 1c DRAM to help data centers reduce electricity costs by up to 30% at a time when the advancement of the AI ​​era is causing an increase in power consumption.

SK Hynix

While throughput has increased by 11 percent compared to the previous generation at 8 Gbps (8,000 MT/s), power efficiency has increased by more than 9 percent.

The confusing DRAM alphabet

Instead of specifying the actual widths of structures in nanometers, DRAM manufacturers now count alphabetically when it comes to new manufacturing processes. Thus, the youngest processes in the so-called “10nm class” are referred to, for example, with a, b and now c.

SK Hynix’s “1c DDR5” is now the sixth generation of the 10nm class, while “1b” is still the fifth generation above. The counting method is based on the fact that early “10nm” processes were called 1x, 1y, and 1z, and then since the switch to EUV, the alphabet practically started from the beginning with 1a, 1b, and 1c.

1c is followed by 1d and then?

It remains to be seen whether the next generation will be called “1d”. After that, a new nomenclature will be required again in the “sub-10nm” class: these processes should be called, for example, 0a, 0b and 0c, as a roadmap from system supplier ASML revealed years ago.

3D DRAM as a technical revolution

Manufacturing processes and confusing names aside, a revolution in DRAM manufacturing is on the horizon in the not-too-distant future. A shift from a planar structure to a 3D design with multiple layers of memory cells is expected around 2030. Similar to the shift from 2D NAND to 3D NAND, this is intended to ensure a further expansion of the areal density. At the same time, the costs that increase with EUV should be reduced again.